`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module: AUDIO_CLK_DIV                                                        //
// Author: Rui Li, modified by Zhiyuan Lin                                      //
// Date: 3/30/2014                                                              //
// Description: This module is to devide the 100MHz by 2.                       //
//////////////////////////////////////////////////////////////////////////////////
module AUDIO_CLK_DIV(CLK_OUT, CLK, Btn_pause, Btn_turbo, Btn_start);
    input CLK, Btn_pause, Btn_turbo, Btn_start;
	 output reg CLK_OUT;
	 reg [1:0] counter_s = 0;
	 reg counter_h = 0;
	 
always @ (posedge CLK) begin
  if(Btn_start == 1) begin
    if(Btn_pause == 0) begin
      if(Btn_turbo == 0) begin
        counter_s <= counter_s + 1'b1;
        CLK_OUT <= counter_s[1];
      end
      else begin
        counter_h <= counter_h + 1'b1;
        CLK_OUT <= counter_h;
      end
    end
    else begin
      CLK_OUT <= 1'b0;
    end
  end
  else begin
    CLK_OUT <= 1'b0;
  end
end

endmodule